1. Field of the Invention
The present invention relates to a high-frequency receiving apparatus and, more specifically, to a high-frequency receiving apparatus receiving and demodulating a high-frequency signal modulated with a digital signal.
2. Description of the Background Art
FIG. 12 is a circuit block diagram of a main portion of a conventional high-frequency receiving apparatus. In FIG. 12, this high-frequency receiving apparatus includes a signal input terminal 31, frequency conversion circuits 32, 33, a 90° phase shifter 34, a local oscillator 35, a PLL circuit 36, a reference signal generation circuit 37, low-pass filters 38, 39, and analog-digital converters 40, 41.
A digitally-modulated high-frequency signal φ 31 is input to signal input terminal 31. High-frequency signal φ 31 is fed to frequency converters 32, 33. In reference signal generation circuit 37, a reference signal having a prescribed frequency is generated. Local oscillator 35 generates a local oscillation signal φ 35 having the same frequency as a center frequency of high-frequency signal φ 31. PLL circuit 36 controls a phase of local oscillation signal φ 35 based on the reference signal generated in reference signal generation circuit 37.
Along with feeding local oscillation signal φ 35 from local oscillator 35 to frequency converter 32, 90° phase shifter 34 generates a signal φ 34 by shifting the phase of local oscillation signal φ 35 by 90°, and feeds to frequency converter 33. Frequency converters 32, 33 mix high-frequency signal φ 31 with respective local oscillation signals φ 35, φ 34 from 90° phase shifter 34, and generate baseband signals φ 32, φ 33.
Low-pass filters 38, 39 remove high-frequency components, interference signals from an adjacent channel, and noise from respective baseband signals φ 32, φ 33 generated at frequency converters 32, 33. Analog-digital converters 40, 41 convert analog signals respectively passed through low-pass filters 38, 39 to digital signals for demodulation processing in a subsequent demodulation unit.
The high-frequency receiving apparatus further includes a complex multiplier 42, digital low-pass filters 43, 44, a phase pull-in circuit 45, a frequency pull-in circuit 46, an adder 47, a numerically controlled oscillator (NCO) 48, and data converters 49, 50. Complex multiplier 42 performs the same operation in a baseband as that of frequency converters 32, 33 which operate in an intermediate frequency band, and converts frequencies of output signals of analog-digital converters 40, 41. Digital low-pass filters 43, 44 remove high-frequency components from output signals of complex multiplier 42. Digital low-pass filters 43, 44 are designed to obtain so-called roll-off properties when combined with a filter characteristic of a sending end. Output signals of digital low-pass filters 43, 44 are fed to a subsequent circuit as an I signal and a Q signal, which are respective demodulation results, and are also fed to phase pull-in circuit 45 and frequency pull-in circuit 46.
Phase pull-in circuit 45 detects phase differences between output signals of digital low-pass filters 43, 44 and a target phase, and feeds a signal having a level corresponding to the phase differences to adder 47. Frequency pull-in circuit 46 detects frequency differences between output signals of digital low-pass filters 43, 44 and a target frequency, and feeds a signal having a level corresponding to the frequency differences to adder 47.
Adder 47 feeds output signals of phase pull-in circuit 45 and frequency pull-in circuit 46 to a control terminal of numerically controlled oscillator 48. Numerically controlled oscillator 48 is formed with a cumulative adder circuit which does not inhibit an overflow, and is set to an oscillation state at a frequency corresponding to a signal value fed to the control terminal. An output signal of numerically controlled oscillator 48 is fed to data converters 49, 50. Data converters 49, 50 respectively generate a sine signal and a cosine signal in response to the output signal of numerically controlled oscillator 48, and feed the results to complex multiplier 42.
Therefore, a digital PLL circuit is formed with complex multiplier 42, digital low-pass filters 43, 44, phase pull-in circuit 45, frequency pull-in circuit 46, adder 47, numerically controlled oscillator 48, and data converters 49, 50, and an oscillation frequency of numerically controlled oscillator 48 is controlled such that, both of the phase difference and frequency difference become zero.
In the conventional high-frequency receiving apparatus, however, because the frequency pull-in range depends on a symbol rate of high-frequency signal φ 31, frequency can be pulled in a relatively wide range when the symbol rate is high, but the pull-in range becomes narrower when the symbol rate is lower.
In a QPSK demodulation system, for example, the frequency difference is calculated from a phase difference between symbols. Therefore, assuming that the symbol rate of high-frequency signal φ 31 is fs, the range in which the frequency difference can be obtained is within ±fs/8. Thus, the frequency pull-in range becomes narrower when symbol rate fs is lower.